Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin-film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Three dimensionally stacked NAND flash memory with a charge trap layer (SiN) has a lateral charge migration issue, where lateral charge migration is expected to cause problems because the charge trap layer is shared between word lines. Lateral charge migration can cause unwanted results in a negative shift of the threshold voltage (VT) and a positive shift of the string read current immediately after programming. See Choi et al., “Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND Flash Memory,” IEEE 2016 Symposium on VLSI Technology Digest of Technical Papers.
It is desirable to provide a structure for three-dimensional integrated circuit memory including a charge trap layer (SiN) without lateral charge migration issues.